DocumentCode
2641815
Title
Partial scan design methods based on internally balanced structure
Author
Takasaki, Tomoya ; Inoue, Tomoo ; Fujiwara, Hideo
Author_Institution
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol., Japan
fYear
1998
fDate
10-13 Feb 1998
Firstpage
211
Lastpage
216
Abstract
In this paper, we theoretically and experimentally show the effectiveness of partial scan design based on internally balanced structure, which is a sequential circuit capable of generating tests with a combinational test generation algorithm. Moreover, we introduce a method of extended partial scan design, which replaces part of not only flip-flops by scan flip-flops but also wires by bypass flip-flops in a sequential circuit, and propose a method of extended partial scan design based on internally balanced structure. Experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented with low area overhead
Keywords
combinational circuits; logic design; logic testing; combinational test generation algorithm; flip-flops; internally balanced structure; partial scan design methods; sequential circuit; Algorithm design and analysis; Benchmark testing; Circuit faults; Circuit testing; Design methodology; Flip-flops; Kernel; Sequential analysis; Sequential circuits; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
0-7803-4425-1
Type
conf
DOI
10.1109/ASPDAC.1998.669448
Filename
669448
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