DocumentCode :
2641862
Title :
A 13.56Mbps PSK receiver for 13.56MHz RFID applications
Author :
van de Beek, R.C.H. ; Ciacci, M. ; Al-Kadi, G. ; Kompan, P. ; Stark, M.
Author_Institution :
NXP Semicond., Eindhoven, Netherlands
fYear :
2012
fDate :
17-19 June 2012
Firstpage :
239
Lastpage :
242
Abstract :
This paper presents a receive chain for very-high bit rate (VHBR) communication over a short range 13.56MHz inductively coupled interface, using multi-bit-per-symbol phase-shift keying (PSK) as proposed for the ISO14443 VHBR amendment. A data rate of up to 13.56Mbps is achieved. The receiver consists of an analog front-end IC followed by an FPGA-based digital baseband processor (DSP). The analog front-end IC recovers the carrier from the antenna signal and performs PSK demodulation using an 8-bit time-to-digital converter (TDC). It consumes 100μA in the 13.56Mbps data rate mode. The FPGA-based DSP´s main functions are symbol clock recovery in a closed-loop with the analog front-end as well as adaptive equalization. Target bit error rates of below 2·10-4 were achieved for transmitted field strengths above 1.2A/m.
Keywords :
VHF antennas; adaptive equalisers; closed loop systems; digital signal processing chips; field programmable gate arrays; phase shift keying; radio receivers; radiofrequency identification; radiofrequency integrated circuits; time-digital conversion; FPGA-based DSP; FPGA-based digital baseband processor; ISO14443 VHBR amendment; PSK demodulation; PSK receiver; RFID applications; TDC; VHBR communication; adaptive equalization; analog front-end IC; analog front-end IC recovers; antenna signal; bit rate 13.56 Mbit/s; data rate; frequency 13.56 MHz; multibit-per-symbol phase-shift keying; short range inductively coupled interface; symbol clock recovery; target bit error rates; time-to-digital converter; transmitted field strengths; very high bit rate communication; Antenna measurements; Clocks; Digital signal processing; Integrated circuits; Phase locked loops; Phase shift keying; Receivers; CMOS; Phase Locked Loops; Phase Shift Keying; Time-to-digital conversion; Wireless communication;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE
Conference_Location :
Montreal, QC
ISSN :
1529-2517
Print_ISBN :
978-1-4673-0413-9
Electronic_ISBN :
1529-2517
Type :
conf
DOI :
10.1109/RFIC.2012.6242272
Filename :
6242272
Link To Document :
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