DocumentCode
2642051
Title
Complete logic family using tunneling-phase-logic devices
Author
Fahmy, Hossam A H ; Kiehl, Richard A.
Author_Institution
Stanford Univ., CA, USA
fYear
1999
fDate
22-24 Nov. 1999
Firstpage
153
Lastpage
156
Abstract
This paper presents the work done to develop and characterize the behavior of binary tunneling phase logic (TPL) devices. Three input NAND, NOR and MINORITY functions are demonstrated using a single TPL element. The fan-out of the gates is discussed as well as the loading effects of multiple gates in cascade. Stable regions of operation are reported and future research possibilities are explored.
Keywords
circuit simulation; integrated logic circuits; logic design; logic gates; logic simulation; tunnelling; MINORITY function; NOR function; binary tunneling phase logic devices; gate fan-out; input NAND function; logic family; multiple gate loading effects; single TPL element; stable operating regions; tunneling-phase-logic devices; CMOS logic circuits; Capacitance; Clocks; Digital circuits; Electrons; Frequency; Logic circuits; Logic devices; Tunneling; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 1999. ICM '99. The Eleventh International Conference on
Print_ISBN
0-7803-6643-3
Type
conf
DOI
10.1109/ICM.2000.884828
Filename
884828
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