CMOS processor circuit design in Hewlett-Packard´s series 700 workstations

Author

Gleason, Craig ; Forsyth, Mark ; Kohlhardt, Charlie ; Mangelsdorf, Steve ; Arnold, Barry ; Luebs, Rick

Author_Institution

Hewlett Packard Co., Fort Collins, CO, USA

fYear

1991

fDate

14-16 Oct 1991

Firstpage

288

Lastpage

292

Abstract

A low cost, high performance implementation of Hewlett-Packard´s PA-RISC 1.1 architecture is described. This chipset is used in HP´s 9000 series 700 workstations. The processor consists of two VLSI chips, a CPU and a floating point coprocessor, which are tightly coupled to large, off-chip instruction and data caches accessed at up to 66 MHz. The CPU is implemented in HP´s 1.0 μm CMOS26 technology and the FPC in Texas Instruments´ 0.8 μm EPIC II CMOS. The caches are implemented using standard asynchronous static RAMs. Features added to improve workstation performance in the areas of graphics and floating point are also described

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; reduced instruction set computing; 0.8 micron; 1 micron; 66 MHz; CMOS processor circuit design; CMOS26 technology; CPU; EPIC II CMOS; Hewlett-Packard´s series 700 workstations; PA-RISC 1.1 architecture; VLSI chips; asynchronous static RAMs; data caches; floating point coprocessor; off-chip instruction; workstation performance; CMOS process; CMOS technology; Circuit synthesis; Coprocessors; Costs; Coupling circuits; Flexible printed circuits; Instruments; Very large scale integration; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-2270-9

Type

conf

DOI

10.1109/ICCD.1991.139900

Filename

139900