An ADC-BiST Scheme Using Sequential Code Analysis

Author

Erdogan, Erdem S. ; Ozev, Sule

Author_Institution

Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysis method is an alternative to histogram based analysis techniques to provide test time improvements, especially when the resources are scarce. In addition to the measurement of DNL and INL, non-monotonic behavior can also be detected with the proposed technique. We present two implementation options based on how much on-chip resources are available. The ramp generator has a high linearity over a full-scale range of IV and the generated ramp signal is capable of testing 13-bit ADCs. The circuit implementation of the ramp generator utilizes a feedback configuration to improve the linearity having an area of 0.017mm² in 0.5mum process

Keywords

analogue-digital conversion; built-in self test; ramp generators; sequential codes; 0.5 micron; 13 bit; DNL measurement; INL measurement; analog to digital converters; built-in self-test scheme; efficient output analysis; histogram based analysis techniques; linear ramp generator; nonmonotonic behavior detection; sequential code analysis; CMOS technology; Circuit testing; Digital signal processing; Histograms; Linearity; Random access memory; Sequential analysis; Signal generators; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364679

Filename

4211884