DocumentCode
2642314
Title
Task Scheduling under Performance Constraints for Reducing the Energy Consumption of the GALS Multi-Processor SoC
Author
Watanabe, Ryo ; Kondo, Masaaki ; Imai, Masashi ; Nakamura, Hiroshi ; Nanya, Takashi
Author_Institution
Res. Center of Adv. Sci. & Technol. (RCAST), Tokyo Univ.
fYear
2007
fDate
16-20 April 2007
Firstpage
1
Lastpage
6
Abstract
The present paper focuses on applications that are periodic and have both latency and throughput constraints. For these applications, pipeline scheduling is effective for reducing energy consumption. Thus, the present paper proposes a pipelined task scheduling method for minimizing the energy consumption of GALS MP-SoC under latency and throughput constraints. First, we model target GALS MP-SoC architecture and application tasks. We then show that the energy optimization problem under this model belongs to the class of mixed-integer linear programming. Next, we propose a new scheduling method based on simulated annealing for the purpose of solving this problem quickly. Finally, experimental results demonstrate that the proposed method achieves a significant energy reduction on a real application under a practical architecture
Keywords
linear programming; minimisation; processor scheduling; simulated annealing; GALS; energy consumption minimization; mixed integer linear programming; multiprocessor SoC; performance constraints; pipelined task scheduling; simulated annealing; Clocks; Delay; Dynamic scheduling; Dynamic voltage scaling; Energy consumption; Frequency; Linear programming; Pipelines; Processor scheduling; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location
Nice
Print_ISBN
978-3-9810801-2-4
Type
conf
DOI
10.1109/DATE.2007.364388
Filename
4211898
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