ALPS: an automatic layouter for pass-transistor cell synthesis

The layout synthesis for pass-transistor cells (PTCs) is different from that for CMOS cells because of the various sizes of transistors used in a PTC and the imbalance in the number of pMOS and nMOS transistors. This makes it difficult to apply commonly used linear transistor placement to PTC layout. Moreover, the mixed placement with CMOS cells restricts the layout freedom of PTCs. Therefore a sandwiched selector structure and pass-transistor graph search are proposed for enabling a multi-row transistor layout and an efficient search algorithm for the diffusion layer sharing problem. Pass-transistor cells generated by ALPS (a_utomatic l_ayouter for p_ass-transistor cell s_ynthesis) are confirmed to have almost the same area density as that of manually designed cells