Multi-access integrated memory management for deeply pipelined processors

In processors with deeply pipelined architecture and numerous buses, management of memory is an important issue. In these processors, each stage of the pipeline might act separately from others, and thus they might have concurrent memory requests. In this paper, we introduce a new method to manage different memory types with multiple sectors in these processors. This method will reduce possible memory conflicts to a minimum and improves performance without using multi-port memory.