DocumentCode :
2642618
Title :
Implementation of a Transaction Level Assertion Framework in SystemC
Author :
Ecker, Wolfgang ; Esen, Volkan ; Hull, M.
Author_Institution :
Infineon Technol. AG, Munich
fYear :
2007
fDate :
16-20 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling
Keywords :
IP networks; integrated circuit design; system-on-chip; IP blocks; RTL; SoC systems; SystemC; assertion based verification; current hardware design; transaction level assertion; verification methodologies; Clocks; Computer architecture; Embedded software; Hardware; Prototypes; Quality assurance; Software prototyping; State-space methods; Synchronization; Virtual prototyping;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364406
Filename :
4211916
Link To Document :
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