DocumentCode
2642814
Title
Testing in the Year 2020
Author
Galivanche, Rajesh ; Kapur, Rohit ; Rubio, Antonio
Author_Institution
Intel Corp., Santa Clara, CA
fYear
2007
fDate
16-20 April 2007
Firstpage
1
Lastpage
6
Abstract
Testing today of a several hundred million transistor system-on-chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What the test technology be like in year 2020 with hundreds of billions of transistors on a single chip? Can we get there with tweaks to today´s technology? While the exact nature of the circuit styles, architectural innovations and product innovations in year 2020 are highly speculative at this point, we examine the impact of likely design and process technology trends on testing methods
Keywords
logic testing; system-on-chip; RF blocks; processor cores; system-on-chip testing; Automatic testing; CMOS technology; Circuit faults; Circuit testing; Integrated circuit testing; Isolation technology; Logic testing; Semiconductor device testing; System testing; Technological innovation;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location
Nice
Print_ISBN
978-3-9810801-2-4
Type
conf
DOI
10.1109/DATE.2007.364417
Filename
4211927
Link To Document