Use of digit-serial computation in systolic arrays

A method is described whereby digit-serial computation can be applied in a fairly general way to a class of systolic arrays so as to cut down substantially the amount of hardware used. Rather than increasing the utilization of the standard processor hardware, the technique proposed allows throughput to be maintained while reducing the hardware by a factor approaching α. The technique is to divide the data words into α sections, or digits, and to process these digits serially. Digit-serial data inherently have a data rate that is an integer submultiple of the parallel data rate, and the digit-size can be chosen so as to meet the data rates required by the systolic algorithm. The advantages of this approach are twofold: the number of wires required for the transmission of data is decreased and the computational elements can be smaller (digit-serial computational elements replacing the standard parallel operators). Thus, the computational elements are fully utilized