Design and implementation of a fast multi-frame hierarchical motion estimation circuit

In this paper, the architecture design and FPGA implementation of a motion estimation (ME) circuit that uses two frames as references is presented. The multi-frame hierarchical motion estimation circuit (MFHME) performs block matching error calculations on the luminance as well as the chrominance components of the pixel data in order to get accurate motion trajectories. The block matching engine of the MFHME is designed based on a hierarchical structure, to reduce total number of calculations while providing accurate motion trajectories. The sum of squared pixel differences (SSD), instead of sum of differences (SAD), has been used as a quality metric in the computation of matching errors for each block. For the 1080p frames, the implementation result shows the MFHME circuit supports a frame rate of 22fps at a frequency of 50 MHZ.