A 0.6–7 Gbps, 1/7 rate, burst mode clock and data recovery circuit and demultiplexer

A 1/7 rate, burst mode clock and data recovery circuit incorporating with demultiplexer is proposed. It covers 622 Mbps to 7 Gbps operation by selective-gating digitally controlled oscillator for phase synchronization and digital frequency-locked loop for frequency tracking. The latency for data recovery and 1:7 demultiplexing is less than 10 bit periods. Incorporating both CDR and demultiplexer, this chip consumes 1.5 mW, 6 mW, and 17 mW respectively at 622 Mbps, 2488Mbps, and 7Gbps operations. Implemented in a 90 nm CMOS technology, the chip area is 1.162 × 1.205 mm².