An Area Optimized Reconfigurable Encryptor for AES-Rijndael

Author

Alam, Monjur ; Ray, Sonai ; Mukhopadhayay, Debdeep ; Ghosh, Santosh ; Roychowdhury, Dipanwita ; Sengupta, Indranil

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

This paper presents a reconfigurable architecture of the advanced encryption standard (AES-Rijndael) cryptosystem. The suggested reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. The work develops a FSMD model based controller which is ideal for such iterative implementation of AES. S-boxes here have been implemented using combinational logic over composite field arithmetic which completely eliminates the need of any internal memory. The design has been implemented on Xilinx Virtex XCV1000 and 0.18mum CMOS technology. The performance of the architecture has been compared with existing results in the literature and has been found to be the most compact implementations of the AES algorithm

Keywords

CMOS logic circuits; combinational circuits; cryptography; field programmable gate arrays; 0.18 micron; AES-Rijndael; CMOS technology; FSMD model; S-box implementation; Xilinx Virtex XCV1000; advanced encryption standard; fully rolled inner-pipelined architecture; reconfigurable encryptor; Arithmetic; CMOS logic circuits; CMOS technology; Computer science; Cryptography; Hardware; NIST; Reconfigurable architectures; Semiconductor device modeling; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364444

Filename

4211954