Title :
Double-Via-Driven Standard Cell Library Design
Author :
Lin, Tsai-Ying ; Lin, Tsung-Han ; Tung, Hui-Hsiang ; Lin, Rung-Bin
Author_Institution :
Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chung-Li
Abstract :
Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a double-via-driven standard cell library design approach to solving this problem. Compared to the results obtained using a commercial cell library, our library on average achieves 78% reduction in dead vias and 95% reduction in dead vials at the expense of 11% increase in total via count. We achieve these results (almost) at no extra cost in total cell area and wire length
Keywords :
cellular arrays; integrated circuit yield; logic design; double-via placement; double-via-driven standard cell library design; manufacturing yield; Bipartite graph; Computer aided manufacturing; Computer science; Costs; Design engineering; Libraries; Pins; Routing; Standards development; Wires;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
DOI :
10.1109/DATE.2007.364460