CHDStd-a model for deep submicron design tools

SEMATECH, a US based consortium of ten major semiconductor manufacturers, is developing a comprehensive system for the design of ICs below .25 μm, which exploits hierarchy, constraint directives, incremental processing, and concurrent design and analysis. This development of SEMATECH´s Chip Hierarchical Design System (CHDS) includes major technological investments in algorithms for design planning, parasitic extraction, and signal integrity verification. The foundation of CHDS is an open design model and API upon which these tools are integrated. This model must support a number of critical requirements including: A data scope that includes connectivity, electrical data, physical data, and timing; Design hierarchy and incremental access to data; A central delay architecture; Efficient, application-selected views of the data. This paper introduces the Integrated Data Model technology being used for CHDS Beta development and its use as the basis for the design of an industry-open specification called the CHDS Technical Data Specification (CHDStd)