Title :
A New Metal Control Gate Last process (MCGL process) for high performance DC-SF (Dual Control gate with Surrounding Floating gate) 3D NAND flash memory
Author :
Noh, Yoohyun ; Ahn, Youngsoo ; Yoo, Hyunseung ; Han, Byeongil ; Chung, Sungjae ; Shim, Keonsoo ; Lee, Keunwoo ; Kwak, Sanghyon ; Shin, Sungchul ; Choi, Iksoo ; Nam, Sanghyuk ; Cho, Gyuseog ; Sheen, Dongsun ; Pyi, Seungho ; Choi, Jongmoo ; Park, Sungkye ;
Author_Institution :
R&D Div., Hynix Semicond. Inc., Icheon, South Korea
Abstract :
A new Metal Control Gate Last process (MCGL process) has been successfully developed for the DC-SF (Dual Control gate with Surrounding Floating gate cell)[1] three-dimensional (3D) NAND flash memory. The MCGL process can realize a low resistive tungsten (W) metal word-line with high-k IPD, a low damage on tunnel oxide/IPD, and a preferable FG shape. And also, a conventional bulk erase can be used, replaced GIDL erase in BiCS[3][4], due to direct connection between channel poly and p-well by the channel contact holes. Therefore, by using MCGL process, high performance and high reliability of DC-SF cell can be achieved for MLC/TLC 256Gb/512Gb 3D NAND flash memories.
Keywords :
flash memories; tungsten; 3D NAND flash memory; GIDL erase; MCGL process; bulk erase; channel contact holes; dual control gate with surrounding floating gate; high performance DC-SF; high-k IPD; low resistive tungsten metal word-line; metal control gate last process; storage capacity 256 Gbit; storage capacity 512 Gbit; Flash memory; Logic gates; Metals; Process control; Resistance; Shape; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242440
