Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

Author

Lin, Kuan Jen ; Fang, Shan Chien ; Yang, Shih Hsien ; Lo, Cheng Chia

Author_Institution

Dept. of Electron. Eng., Fu Jen Catholic Univ.

fYear

2007

fDate

16-20 April 2007

Firstpage

1

Lastpage

6

Abstract

Cryptographic embedded systems are vulnerable to differential power analysis (DPA) attacks. This paper propose a logic design style, called as pre-charge masked Reed-Muller logic (PMRML) to overcome the glitch and dissipation timing skew (DTS) problems in design of DPA-resistant cryptographic hardware. Both problems can significantly reduce the DPA-resistance. To our knowledge, the DTS problem and its countermeasure have not been reported. The PMRML design can be fully realized using common CMOS standard cell libraries. Furthermore, it can be used to implement universal functions since any Boolean function can be represented as the Reed-Muller form. An AES encryption module was implemented with multi-stage PMRML. The results show the efficiency and effectiveness of the PMRML design methodology

Keywords

Boolean functions; CMOS integrated circuits; cryptography; embedded systems; logic design; AES encryption module; Boolean function; CMOS standard cell libraries; DPA-resistant; cryptographic embedded systems; cryptographic hardware; differential power analysis; dissipation timing skews; glitches; logic design; pre-charge masked Reed-Muller logic; CMOS logic circuits; Cryptography; Design methodology; Embedded system; Energy consumption; Hardware; Libraries; Logic design; Timing; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07

Conference_Location

Nice

Print_ISBN

978-3-9810801-2-4

Type

conf

DOI

10.1109/DATE.2007.364471

Filename

4211981