DocumentCode
2643761
Title
Worst-Case Design and Margin for Embedded SRAM
Author
Aitken, Robert ; Idgunji, Sachin
Author_Institution
ARM, Sunnyvale, CA
fYear
2007
fDate
16-20 April 2007
Firstpage
1
Lastpage
6
Abstract
An important aspect of design for yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previously, this has involved multiple simulation corners and extreme test conditions. It is shown that statistical concerns and device variability now require a different approach, based on work in extreme value theory. This method is used to develop a lower-bound for variability-related yield in memories
Keywords
SRAM chips; embedded systems; integrated circuit yield; design for yield; embedded SRAM; extreme value theory; variability-related yield; worst-case design; Circuit simulation; Product design; Random access memory; Robustness; Stress; Temperature sensors; Testing; Threshold voltage; Timing; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location
Nice
Print_ISBN
978-3-9810801-2-4
Type
conf
DOI
10.1109/DATE.2007.364475
Filename
4211985
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