A hardware-efficient VLSI implementation of a 4-channel ICA processor for biomedical signal measurement

Author

Chen, Chiu-Kuo ; Chua, Ericson ; Fu, Chih-Chung ; Tseng, Shao-Yen ; Fang, Wai-Chi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2011

fDate

9-12 Jan. 2011

Firstpage

607

Lastpage

608

Abstract

This paper presents a 4-channel ICA implementation in the separation of EEG signals for on-line monitoring and analysis of brain functionalities. A novel ICA architecture utilizing mixed sequential, pipelined, and parallel processing units and employing interleaved and circular-based RAM modules to achieve hardware-efficient design is presented. The ICA processor is fabricated using UMC 90nm High-Vt CMOS technology.

Keywords

CMOS memory circuits; VLSI; biomedical equipment; brain; electroencephalography; independent component analysis; integrated circuit design; medical signal processing; microprocessor chips; modules; parallel processing; pipeline processing; random-access storage; source separation; EEG signals; UMC high-voltage CMOS technology; biomedical signal measurement; brain functionalities; circular-based RAM modules; four-channel ICA processor; hardware-efficient VLSI implementation; independent component analysis; mixed sequential processing units; on-line monitoring; parallel processing units; pipelined processing units; size 90 nm; Computer architecture; Correlation; Electroencephalography; Field programmable gate arrays; Hardware; Random access memory; Training;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics (ICCE), 2011 IEEE International Conference on

Conference_Location

Las Vegas, NV

ISSN

2158-3994

Print_ISBN

978-1-4244-8711-0

Type

conf

DOI

10.1109/ICCE.2011.5722766

Filename

5722766