DocumentCode
2643791
Title
The design of an asynchronous VHDL synthesizer
Author
Tan, Sun-Yen ; Furber, Stephen B. ; Yen, Wen-Fang
Author_Institution
Dept. of Comput. Sci., Manchester Univ., UK
fYear
1998
fDate
23-26 Feb 1998
Firstpage
44
Lastpage
51
Abstract
This paper presents a straightforward approach for synthesizing a standard VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on `micropipelines´, a style currently used to develop asynchronous microprocessors at Manchester University. The rules of partition and conversion which are used to implement the synthesizer are also described. The synthesizer greatly reduces the design time of a complex micropipeline circuit
Keywords
asynchronous circuits; hardware description languages; high level synthesis; pipeline processing; asynchronous VHDL synthesizer; asynchronous circuit design; complex micropipeline circuit; conversion rules; micropipelines; partition rules; standard VHDL description; Asynchronous circuits; Circuit synthesis; Computer science; Hardware; Integrated circuit interconnections; Logic circuits; Microprocessors; Protocols; Synthesizers; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655835
Filename
655835
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