Title :
Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture
Author :
Tsuji, Y. ; Nebashi, R. ; Sakimura, N. ; Morioka, A. ; Honjo, H. ; Tokutome, K. ; Miura, S. ; Suzuki, T. ; Fukami, S. ; Kinoshita, K. ; Hanyu, T. ; Endoh, T. ; Kasai, N. ; Ohno, H. ; Sugibayashi, T.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
A spintronics primitive gate with redundancy was designed using domain wall motion (DWM) cells, and the data-missing rate was drastically improved to ~6 (Perror)2 when the error rate per DWM cell was Perror. All the DWM cells aligned in series were written simultaneously, which suppressed the increase in power consumption when writing. Application of 4-terminal DWM cells with physically separated current paths for writing and reading saved extra path transistors for redundancy and there were no area overheads.
Keywords :
logic circuits; memory architecture; power consumption; domain wall motion cells; error rate per DWM cell; extra path transistors; high error correction efficiency; logic-in memory architecture; power consumption; spintronics primitive gate; Error analysis; Logic gates; Magnetic domain walls; Magnetic tunneling; Magnetoelectronics; Redundancy; Resistance;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242462
