Title :
Development of an ASIP Enabling Flows in Ethernet Access Using a Retargetable Compilation Flow
Author :
Van Renterghem, K. ; Demuytere, P. ; Verhulst, D. ; Vandewege, J. ; Qiu, Xing-Zhi
Author_Institution :
Dept. of Inf. Technol., Ghent Univ., Gent
Abstract :
In this paper we research an FPGA based application specific instruction set processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a fully optimized ASIP with a VLIW instruction set which allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment
Keywords :
application specific integrated circuits; instruction sets; local area networks; processor scheduling; ASIP; Ethernet access; VLIW instruction set; application specific instruction set processor; retargetable compilation flow; Access protocols; Application specific processors; Data mining; Ethernet networks; Field programmable gate arrays; Multicore processing; Payloads; Process design; Traffic control; Transport protocols;
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
DOI :
10.1109/DATE.2007.364497
