Title :
A 32nm high-k and metal-gate anti-fuse array featuring a 1.01µm2 1T1C bit cell
Author :
Kulkarni, Sarvesh H. ; Pae, Sangwoo ; Chen, Zhanping ; Hafez, Walid ; Pedersen, Brian ; Rahman, Anisur ; Tong, Tom ; Bhattacharya, Uddalak ; Jan, Chia-Hong ; Zhang, Kevin
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR, USA
Abstract :
A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC process technology enables smallest reported one-transistor one-capacitor (1T1C) bit cell area measuring 1.01μm2. The 32-row by 32-column array with a programmable sensing scheme demonstrates yield exceeding 99.9% and robust reliability.
Keywords :
CMOS memory circuits; integrated circuit reliability; read-only storage; 1T1C bit cell; CMOS process; anti-fuse memory; high-density OTP; high-k anti-fuse array; metal-gate anti-fuse array; one time programmable-ROM array; one-transistor one-capacitor bit cell; robust reliability; Arrays; Capacitors; Electric breakdown; Logic gates; Programming; Sensors; High-density anti-fuse; high-k metal-gate;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242470
