ATM cell modelling using objective VHDL

High potentialities in terms of abstraction and reuse for hw design are offered by the recently proposed innovative extensions to VHDL, implementing object-oriented techniques. In this paper we evaluate the results of modelling ATM cells in Objective VHDL, exploiting the language features in terms of abstraction and reuse. The selected modules are representatives of highly used components for a wide range of multimedia applications. Entity-architecture classes and abstract data types are considered. Users methodology and benefits are highlighted. The results can be easily extended to other domains where hw design is involved