Computer simulation of IGBT losses in PFC circuits

Author

Stuart, Thomas A. ; Ye, Shaoyan

Author_Institution

Toledo Univ., OH, USA

fYear

1994

fDate

7-10 Aug 1994

Firstpage

85

Lastpage

90

Abstract

An analysis is presented that forms the basis of an algorithm for calculating the IGBT losses in a power factor correction (PFC) circuit. The method employs experimental data from an offline test circuit that closely resembles the switching conditions in an actual PFC. This technique provides calculated values of both the conduction and switching losses of the main transistor in a boost-type PFC circuit. Experimental results for a 6 kW PFC are also included

Keywords

DC-DC power convertors; bipolar transistor switches; circuit analysis computing; circuit testing; digital simulation; insulated gate bipolar transistors; losses; power bipolar transistors; power engineering computing; power factor correction; power semiconductor switches; semiconductor device models; semiconductor device testing; switching circuits; 6 kW; IGBT losses; algorithm; boost power convertor; computer simulation; conduction losses; experimental data; offline test circuit; power factor correction; switching losses; Computer simulation; FETs; Filters; Frequency synchronization; Insulated gate bipolar transistors; Pulse circuits; Shape; Switches; Switching frequency; Switching loss;

fLanguage

English

Publisher

ieee

Conference_Titel

Computers in Power Electronics, 1994., IEEE 4th Workshop on

Conference_Location

Trois-Rivieres, Que.

Print_ISBN

0-7803-2091-3

Type

conf

DOI

10.1109/CIPE.1994.396734

Filename

396734