An ultra-thin interposer utilizing 3D TSV technology

Author

Chiou, W.C. ; Yang, K.F. ; Yeh, J.L. ; Wang, S.H. ; Liou, Y.H. ; Wu, T.J. ; Lin, J.C. ; Huang, C.L. ; Lu, S.W. ; Hsieh, C.C. ; Teng, H.A. ; Chiu, C.C. ; Chang, H.B. ; Wei, T.S. ; Lin, Y.C. ; Chen, Y.H. ; Tu, H.J. ; Ko, H.D. ; Yu, T.H. ; Hung, J.P. ; Tsai,

Author_Institution

R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan

fYear

2012

fDate

12-14 June 2012

Firstpage

107

Lastpage

108

Abstract

To achieve ultra small form factor package solution, an ultra-thin (50μm) Si interposer utilizing through-silicon-via (TSV) technology has been developed. Challenges associated with handling thin wafer and maintaining package co-planarity have been overcome to stack thin dies (200 μm) on ultra-thin interposer. Improved electrical performance and the advantages of this innovative thin interposer are highlighted in this paper. Warpage behavior is investigated with simulation and experiments to ensure reliability and robustness of the Si stack. Reduction in package thickness is realized to achieve high functionality, small form factor, better electrical performance and robust reliability by stacking thin dies on ultra-thin interposer.

Keywords

elemental semiconductors; integrated circuit packaging; integrated circuit reliability; silicon; three-dimensional integrated circuits; 3D TSV technology; Si; package co-planarity; package solution; reliability; size 50 mum; stacking thin dies; thin wafer; through-silicon-via; ultra small form factor; ultra-thin silicon interposer; warpage behavior; Assembly; Copper; Resistance; Silicon; Stacking; Stress; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242484

Filename

6242484