Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates

Author

Fenouillet-Beranger, C. ; Perreau, P. ; Weber, O. ; Ben-Akkez, I. ; Cros, A. ; Bajolet, A. ; Haendler, S. ; Fonteneau, P. ; Gouraud, P. ; Richard, E. ; Abbate, F. ; Barge, D. ; Pellissier-Tanon, D. ; Dumont, B. ; Andrieu, F. ; Passieux, J. ; Bon, R. ; Bar

Author_Institution

LETI MINATEC, CEA, Grenoble, France

fYear

2012

fDate

12-14 June 2012

Firstpage

115

Lastpage

116

Abstract

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530μA/μm @ Ioff=100nA/μm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12μm² bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

Keywords

CMOS integrated circuits; electrostatic discharge; elemental semiconductors; leakage currents; modulation; silicon; silicon-on-insulator; CMOS device; FDSOI-bulk technology; NMOS; Si; UTBOX sSOI substrate; cell current improvement; hybrid ESD device; ion boost; leakage current reduction; size 1.5 nm; size 25 nm; size 30 nm; standard UTBB SOI; threshold voltage modulation; voltage 1 V; Degradation; Logic gates; MOS devices; Performance evaluation; Silicon on insulator technology; Standards; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242488

Filename

6242488