DocumentCode :
2644537
Title :
A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality
Author :
Pan, Sung-Jui ; Cheng, Kwang-Ting
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA
fYear :
2007
fDate :
16-20 April 2007
Firstpage :
1
Lastpage :
6
Abstract :
The failure rate, the sources of failures and the test costs for nanometer devices are all increasing. Therefore, to create a reliable system-on-a-chip device requires designers to implement fault tolerance. However, while system-level fault tolerance could significantly relax the quality requirements of the system´s building blocks, every fault-tolerant scheme only works under certain failure mechanisms and within a certain range of error probabilities. Also, designing a system with a high failure-rate component could be very expensive because the growth rate of the design complexity and the system overhead for fault tolerance could be significantly greater than the component failure rate. Therefore, it is desirable to understand the trade-offs between component test quality and system fault-tolerant capability for achieving the desired reliability under cost constraints. In this paper, the authors propose an analysis framework for system reliability considering (a) the test quality achieved by manufacturing testing, on-line self-checking, and off-line built-in self-test; (b) the fault-tolerant and spare schemes; and (c) the component defect and error probabilities. The authors demonstrate that, through proper redundancy configurations and low-cost testing to insure a certain degree of component test quality, a low-redundant system might achieve equal or higher reliability than a high-redundant system
Keywords :
built-in self test; fault tolerance; integrated circuit reliability; integrated circuit testing; nanotechnology; system-on-chip; built-in self-test; component test quality; error tolerance; failure rate; fault tolerance; manufacturing testing; nanometer devices; on-line self-checking; system overhead; system reliability analysis; system-on-chip; Automatic testing; Costs; Error probability; Failure analysis; Fault tolerant systems; Nanoscale devices; Pulp manufacturing; Reliability; System testing; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition, 2007. DATE '07
Conference_Location :
Nice
Print_ISBN :
978-3-9810801-2-4
Type :
conf
DOI :
10.1109/DATE.2007.364527
Filename :
4212037
Link To Document :
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