Title :
Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty
Author :
Miki, H. ; Yamaoka, M. ; Frank, D.J. ; Cheng, K. ; Park, D. -G ; Leobandung, Effendi ; Torii, K.
Author_Institution :
Semicond. Innovation Res. Project, Hitachi America, Ltd., Yorktown Heights, NY, USA
Abstract :
This paper analyzes the extensive variability of random telegraph noise (RTN) responses to gate voltage and temperature in undoped nanoscale nFETs. Using comprehensive RTN measurements to extract the response parameters of >;600 traps, we show that the RTN can induce delay uncertainty in dense low power (i.e., narrow devices and low VDD) 14-nm technology that may exceed 50% of the nominal delay.
Keywords :
delays; field effect transistors; logic gates; random noise; silicon-on-insulator; RTN response; Voltage dependence; gate voltage; highly scaled HKMG ETSOI nFET; logic delay uncertainty; random telegraph noise; size 14 nm; temperature dependence; undoped nanoscale nFET; Acceleration; Couplings; Delay; FETs; Histograms; Logic gates; Temperature dependence;
Conference_Titel :
VLSI Technology (VLSIT), 2012 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4673-0846-5
Electronic_ISBN :
0743-1562
DOI :
10.1109/VLSIT.2012.6242499
