DocumentCode :
2644788
Title :
Cost effective H-V scaling direction interchangeable frame-lock scaling engine
Author :
Huang, Chung-Hsun ; Chang, Chao-Yang
Author_Institution :
Inst. of Electr. Eng., Nat. Chung Cheng Univ., Chiayi, Taiwan
fYear :
2011
fDate :
9-12 Jan. 2011
Firstpage :
711
Lastpage :
712
Abstract :
This paper proposes a cost effective frame-lock scaling engine to reduce the embedded memory size. The key technique is the H-V scaling direction interchangeable architecture. Evaluation results show that the proposed design can reduce 76% and 10% embedded memory requirements as compared with two types of conventional scaling engine.
Keywords :
image resolution; image sequences; H-V scaling directions; embedded memory size; frame-lock scaling engine; image resolution; interchangeable architecture; Clocks; Engines; Interpolation; Memory management; Pixel; Synchronization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location :
Las Vegas, NV
ISSN :
2158-3994
Print_ISBN :
978-1-4244-8711-0
Type :
conf
DOI :
10.1109/ICCE.2011.5722823
Filename :
5722823
Link To Document :
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