High-aspect ratio through silicon via (TSV) technology

Author

Chang, H.B. ; Chen, H.Y. ; Kuo, P.C. ; Chien, C.H. ; Liao, E.B. ; Lin, T.C. ; Wei, T.S. ; Lin, Y.C. ; Chen, Y.H. ; Yang, K.F. ; Teng, H.A. ; Tsai, W.C. ; Tseng, Y.C. ; Chen, S.Y. ; Hsieh, C.C. ; Chen, M.F. ; Liu, Y.H. ; Wu, T.J. ; Hou, Shang Y. ; Chiou, W

Author_Institution

Integrated Interconnect & Packaging Div., Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan

fYear

2012

fDate

12-14 June 2012

Firstpage

173

Lastpage

174

Abstract

The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 μm × 30 μm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 μm × 30 μm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation of TSV stress is correlated with minimized keep-out zone (KOZ). The achievement of excellent performance of 3D-IC yield and high aspect ratio TSV embedded device characteristics are key milestones in the promising manufacturability of 3D-IC by silicon foundry technology.

Keywords

CMOS integrated circuits; copper; embedded systems; integrated circuit yield; silicon; stress relaxation; thermal expansion; three-dimensional integrated circuits; 3D-IC yield; CMOS chip; Cu; KOZ; Si; TSV dimension; TSV process; TSV technology; electrical performance; embedded device characteristics; high-aspect ratio; keep-out zone; size 28 nm; stress relaxation; thermal expansion; through silicon via; MOSFET circuits; MOSFETs; Performance evaluation; Silicon; Strain; Stress; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2012 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4673-0846-5

Electronic_ISBN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2012.6242517

Filename

6242517