Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results

A detailed comparison between III-V TFET´s experimental characteristics and atomistic quantum mechanical predictions is reported to study the validity of the performance improvement predictions of a scaled TFET. Simulations did not employ any fitting parameters to match the experimental data, but instead used material and geometry parameters as the only inputs. The results show that the experimental and simulation characteristics are in reasonable agreement, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability. The differences between scaled TFET predictions and large experimental TFET devices are shown to be due to the geometry, meaning that improved electrostatics with thin body and double-gate (DG) is required for TFET scaling. Results demonstrate that the III-V TFET is a realistic candidate for future low-voltage logic applications.