Title :
VHDL modelling and analysis of fault secure systems
Author :
Coppens, Jason ; Al-Khalili, Dhamin ; Rozon, Côme
Author_Institution :
Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada
Abstract :
This paper presents an analysis process targeted for the verification of fault secure systems during their design phase. This process deals with a realistic set of micro-defects at the device level which are mapped into mutant and saboteur based VHDL fault models in the form of logical and/or performance degradation faults. Automatic defect injection and simulation are performed through a VHDL test bench. Extensive post processing analysis is performed to determine defect coverage, figure of merit for fault secureness, and MTTF
Keywords :
failure analysis; hardware description languages; high level synthesis; MTTF; VHDL model; automatic defect injection; defect coverage; design; fault secure system; figure of merit; logical degradation; micro-defects; performance degradation; post processing analysis; simulation; verification; Circuit faults; Circuit simulation; Circuit testing; Hardware; Integrated circuit technology; Logic testing; Military computing; Security; Statistical analysis; Statistics;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655849
