Heterogeneous BISR-approach using system level synthesis flexibility

We propose a novel methodology for designing fault-tolerant real-time system to achieve optimal productivity on a single-chip multiprocessor platform using the heterogeneous built-in-self-repair (BISR) based graceful degradation and yield enhancement technique as an embedded optimization engine which exploits task-level scheduling and algorithm selection flexibility. We also developed a hardware fault model for modern superscalar processors and multi-processors which enables an efficient treatment of the synthesis and compilation goals