Title :
Algorithms for detailed placement of standard cells
Author_Institution :
Res. Inst. for Discrete Math., Bonn Univ., Germany
Abstract :
The state-of-the-art methods for the placement of large-scale standard cell designs work in a top-down fashion. After some iterations, where more and more detailed placement information is obtained, a final procedure for finding a legal placement is needed. This paper presents a new method for this final task, based on efficient algorithms from combinatorial optimization
Keywords :
circuit layout CAD; circuit optimisation; integrated circuit layout; IC layout; combinatorial optimization; detailed placement; large-scale standard cell designs; standard cells placement; top-down fashion; Algorithm design and analysis; Circuits; Constraint optimization; Design optimization; Law; Legal factors; Mathematics; Partitioning algorithms; Timing; Wiring;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655875
