Power-simulation of cell based ASICs: accuracy- and performance trade-offs

Author

Rabe, Dirk ; Jochens, Gerd ; Kruse, Lars ; Nebel, Wolfgang

Author_Institution

Dept. of Comput. Sci., Oldenburg Univ., Germany

fYear

1998

fDate

23-26 Feb 1998

Firstpage

356

Lastpage

361

Abstract

Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at high performance. The high accuracy is achieved by putting emphasis on delay- and power-modelling. The impact of these modelling factors on accuracy and performance is demonstrated by comparing GliPS to other tools on circuit-level and a simple toggle count based power simulator TPS on gate level

Keywords

application specific integrated circuits; cellular arrays; delays; digital simulation; integrated circuit modelling; logic CAD; logic gates; GliPS; TPS; cell based ASICs; circuit-level; delay-modelling; gate level; gate-level power-simulation tool; glitch power simulator; modelling factors; performance trade-offs; power-modelling; toggle count based power simulator; transistor-level simulators; Application specific integrated circuits; Circuit simulation; Computational modeling; Computer science; Computer simulation; Delay estimation; Energy consumption; Hardware design languages; Integrated circuit reliability; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655882

Filename

655882