Array based architecture for EZW image encoding on FPGA using Handel-C

Real-time image compression is usually a core operation in many embedded applications. Often in such applications, high throughputs are required. In this paper, we propose an array-based architecture for hardware implementation of an EZW encoder to achieve high throughputs. It exploits the inherent properties of parallelism exhibited by the EZW algorithm and also the spatial correlation properties of the DWT coefficients. Every spatial tree is generated and stored independently in memory blocks of an array and each of them subject to EZW separately through an array of processing elements. This architecture is implemented on FPGA using Handel-C and the resource utilization is presented.