DocumentCode :
2645881
Title :
A constraint driven approach to loop pipelining and register binding
Author :
Mesman, Bart ; Strik, Marino ; Timmer, Adwin H. ; Van Meerbergen, Jef L. ; Jess, Jochen A G
Author_Institution :
Philips Res. Lab., Eindhoven, Netherlands
fYear :
1998
fDate :
23-26 Feb 1998
Firstpage :
377
Lastpage :
383
Abstract :
Code generation methods for DSP applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms, and resource constraints imposed by a hardware architecture. In this paper we present a method for register binding and instruction scheduling based on the exploitation and analysis of resource and timing constraints. The analysis identifies sequencing constraints between operations additional to the precedence constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing, resource and register constraints. The presented approach results in an efficient method of obtaining high quality instruction schedules with low register requirements
Keywords :
constraint handling; digital signal processing chips; pipeline processing; processor scheduling; program compilers; resource allocation; timing; DSP applications; code generation methods; constraint driven approach; hardware architecture; instruction scheduling; loop pipelining; performance requirements; precedence constraints; register binding; register requirements; resource constraints; sequencing constraints; timing constraints; Added delay; Clocks; Costs; Delay effects; Pipeline processing; Registers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
Type :
conf
DOI :
10.1109/DATE.1998.655885
Filename :
655885
Link To Document :
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