Optimal temporal partitioning and synthesis for reconfigurable architectures

Author

Kaul, Meenakshi ; Vemuri, Ranga

Author_Institution

Dept. of Electr. Comput. & Eng. Comput. Syst., Cincinnati Univ., OH, USA

fYear

1998

fDate

23-26 Feb 1998

Firstpage

389

Lastpage

396

Abstract

We develop a 0-1 non-linear programming (NLP) model for combined temporal partitioning and high-level synthesis from behavioral specifications destined to be implemented on reconfigurable processors. We present tight linearizations of the NLP model. We present effective variable selection heuristics for a branch and bound solution of the derived linear programming model. We show how tight linearizations combined with good variable selection techniques during branch and bound yield optimal results in relatively short execution times

Keywords

high level synthesis; integer programming; logic partitioning; nonlinear programming; processor scheduling; reconfigurable architectures; temporal logic; 0-1 nonlinear programming model; behavioral specifications; branch and bound solution; effective variable selection heuristics; execution times; high-level synthesis; optimal temporal partitioning; reconfigurable architectures; tight linearizations; variable selection techniques; Contracts; Field programmable gate arrays; Hardware; Input variables; Laboratories; Linear programming; Military computing; Permission; Reconfigurable architectures; Scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Design, Automation and Test in Europe, 1998., Proceedings

Conference_Location

Paris

Print_ISBN

0-8186-8359-7

Type

conf

DOI

10.1109/DATE.1998.655887

Filename

655887