An integrated flow for technology remapping and placement of sub-half-micron circuits

This paper presents a new design flow, FPD-SiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic partitioning, floorplanning, global routing, and timing analysis/budgeting steps, followed by technology remapping and detailed placement of the selected logic clusters. The strength of the approach lies in the dynamic programming-based algorithm, SiMPA-D, used for performing simultaneous technology mapping and linear placement of logic clusters. This algorithm generates a set of solutions for each cluster, all of which are noninferior (in terms of gate area, cutwidth and delay), and hence permits trade-offs between total area (gate plus wiring) and total delay (gate plus wiring). Experimental results from a large number of MCNC benchmarks have proved the effectiveness of the proposed flow