• DocumentCode
    26460
  • Title

    A 10-bit 110 kS/s 1.16 \\mu\\hbox {W} SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

  • Author

    Taherzadeh-Sani, Mohammad ; Lotfi, Reza ; Nabki, Frederic

  • Author_Institution
    Dept. of Electr. Eng., Ferdowsi Univ. of Mashhad, Mashhad, Iran
  • Volume
    61
  • Issue
    8
  • fYear
    2014
  • fDate
    Aug. 2014
  • Firstpage
    584
  • Lastpage
    588
  • Abstract
    A 10-bit 110-kS/s successive-approximation analog-to-digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, a low-complexity calibration technique, a hybrid single/differential digital-to-analog converter architecture, and an attenuation capacitor with low sensitivity to mismatch errors. Fabricated in 180-nm CMOS, this ADC consumes a total power of 1.16 μW from 1.5 V/1.2 V analog/digital power supplies. The integral nonlinearity is between -1.23 LSB and 1.19 LSB, whereas the differential nonlinearity is between -0.71 LSB and 0.92 LSB. The ADC signal-to-noise-and-distortion ratio and spurious-free dynamic range are 56.1 and 67 dB with a 39.5-kHz sinusoid input, respectively. The ADC figure-of-merit is of 20 fJ per conversion step, which is very competitive, as compared with state-of-the-art ADCs in similar 180-nm CMOS technologies.
  • Keywords
    CMOS digital integrated circuits; analogue-digital conversion; biomedical electronics; digital-analogue conversion; low-power electronics; CMOS technology; SA-ADC; analog-digital power supplies; attenuation capacitor; differential nonlinearity; frequency 39.5 kHz; hybrid single-differential digital-to-analog converter DAC architecture; integral nonlinearity; low-complexity calibration technique; low-power operation; multichannel biomedical applications; power 1.16 muW; reduced-speed dynamic comparator; signal-to-noise-and-distortion ratio; size 180 nm; spurious-free dynamic range; successive-approximation analog-to-digital converter; voltage 1.5 V; word length 10 bit; Attenuation; CMOS integrated circuits; Calibration; Capacitors; Clocks; Noise; Power demand; CMOS integrated circuits; low power; multichannel recording systems; reduced area; successive-approximation-register analog-to-digital converters (SAR ADCs);
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2014.2327373
  • Filename
    6823161