Title :
Reduced Hamming count and its aliasing probability
Author :
Gleason, Anita ; Jone, Wen-Ben
Author_Institution :
Dept. of Comput. Sci., New Mexico Polytech., Socorro, NM, USA
Abstract :
Hardware overhead reduction through counter selection is considered for the Hamming count compaction test. A method to choose the most effective syndrome and input variable counter pair is given. Both simulation and theoretical analysis illustrate that this method produces an optimal pairing. The aliasing probability of this two-counter test is developed and shown to reduce the exhaustive ones count aliasing probability by half an order
Keywords :
logic testing; aliasing probability; compaction test; counter selection; hardware overhead reduction; optimal pairing; reduced Hamming count; simulation; two-counter test; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Computer science; Counting circuits; Fault detection; Hardware; Probability;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-2270-9
DOI :
10.1109/ICCD.1991.139918
