On-line IEEE floating-point multiplication and division for reduced power dissipation

We propose implementations for on-line IEEE floating-point (FP) multiplication and division. In on-line arithmetic a result is computed digit-serially (most significant digits first). On-line implementations are well known for fixed-point operands, where they allow for significant reductions in power dissipation and implementation costs. Online arithmetic on IEEE FP numbers imposes challenges beyond the implementation of on-line fixed-point arithmetic. These challenges particularly include the simultaneous computation of normalization and IEEE compliant rounding in an on-line schedule. We show how these challenges can be solved efficiently for the implementation of on-line IEEE floating-point (FP) multiplication and division. The proposed designs extend the design space for IEEE compliant floating-point implementations in the direction of low implementation cost and reduced power dissipation. The proposed implementations are fully compliant with the IEEE 754 FP standard.