Title :
Estimation of the defective IDDQ caused by shorts in deep-submicron CMOS ICs
Author :
Rodríguez-Montañés, R. ; Figueras, J.
Author_Institution :
Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The defective IDDQ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation current of a simple MOSFET, a lower bound of IDDQ defective consumption versus Leff is found. Quiescent current consumption lower bound for shorts intragate, and shorts intergate affecting at least one logic node is evaluated. The methodology is used to estimate the IDDQ distribution, for a given input vector, of defective circuits. This IDDQ estimation allows the determination of the threshold value to be used for the faulty/fault-free circuit classification
Keywords :
CMOS digital integrated circuits; carrier mobility; integrated circuit modelling; integrated circuit reliability; short-circuit currents; IDDQ distribution; MOSFET saturation current; carrier mobility degradation; deep-submicron CMOS ICs; defective IDDQ estimation; defective circuits; faulty/fault-free circuit classification; full complementary MOS circuits; geometry reductions; high performance scenario; intergate shorts; intragate shorts; low power scenario; power supply voltage reduction; quiescent current consumption lower bound; saturation current characterisation; technology scaling; transistor dimensions; velocity saturation; Bridge circuits; CMOS technology; Circuit testing; Degradation; Geometry; Logic; MOSFET circuits; Power supplies; Solid modeling; Voltage;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655903
