DocumentCode
2646357
Title
Performance-manufacturability tradeoffs in IC design
Author
Heineken, Hans T. ; Maly, Wojciech
Author_Institution
Level One Commun., Sacramento, CA, USA
fYear
1998
fDate
23-26 Feb 1998
Firstpage
563
Lastpage
567
Abstract
Traditional VLSI design objectives are to minimize time-to-first-silicon while maximizing performance. Such objectives lead to designs which are not optimum from a manufacturability perspective. The objective of this paper is to illustrate the above claim by performing performance/manufacturability tradeoff analysis. The basis for such an analysis, in which the relationship between a product´s clock frequency and wafer productivity is modeled, is described in detail. New applied yield models are discussed as well
Keywords
VLSI; design for manufacture; integrated circuit design; integrated circuit layout; integrated circuit yield; IC design; VLSI design; clock frequency; performance-manufacturability tradeoffs; wafer productivity; yield models; Area measurement; Clocks; Costs; Frequency; Integrated circuit layout; Integrated circuit modeling; Particle measurements; Productivity; Pulp manufacturing; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655914
Filename
655914
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