DocumentCode
2646452
Title
Optimal synthesis of digital counter
Author
Javan, H. ; Rayaravivarma, V.
Author_Institution
North Carolina A&T State Univ., Greensboro, NC, USA
fYear
1996
fDate
25-27 Jun 1996
Firstpage
438
Lastpage
442
Abstract
This paper presents a unified and systematic approach to the analysis and synthesis of digital counters. Our method consists, firstly of analysing a given 3 bit counter to develop the state diagram and to investigate the possibility of hangup states. Based on this, we then synthesized a given logic function. Different synthesis methods are discussed, compared, and finally, an optimum circuit meeting the design specifications is selected
Keywords
counting circuits; flip-flops; logic design; counter analysis; design specifications; digital counter; hangup states; logic function; optimal synthesis; state diagram; Circuit synthesis; Counting circuits; Digital circuits; Flip-flops; Impedance; Java; Logic functions; Network synthesis; Timing; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Southcon/96. Conference Record
Conference_Location
Orlando, FL
ISSN
1087-8785
Print_ISBN
0-7803-3268-7
Type
conf
DOI
10.1109/SOUTHC.1996.535107
Filename
535107
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