Title :
Processor-based decoupled PDP timing controller design
Author :
Na, Yeoul ; Hwang, Seok Joong ; Lee, Cheol Ho ; Min, Junkyu ; Kim, Taejin ; Kim, Seon Wook
Abstract :
This paper presents an efficient design of a processor-based PDP timing controller that supports multiple high frequency control signal channels in multi-clock domain. We implemented a prototype system using the proposed design on FPGA attached to 42-inch and 50-inch PDP panels with HD resolution.
Keywords :
field programmable gate arrays; microprocessor chips; plasma displays; FPGA; HD resolution; PDP panels; field programmable gate array; high frequency control signal channels; multiclock domain; plasma display panel; processor-based decoupled PDP timing controller design; Control systems; Field programmable gate arrays; Process control; Prototypes; Pulse width modulation; Random access memory; Timing;
Conference_Titel :
Consumer Electronics (ICCE), 2011 IEEE International Conference on
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-8711-0
DOI :
10.1109/ICCE.2011.5722909
