Title :
Sequential equivalence checking without state space traversal
Author :
van Eijk, C.A.J.
Author_Institution :
Sect. of Design Autom., Eindhoven Univ. of Technol., Netherlands
Abstract :
Because general algorithms for sequential equivalence checking require a state space traversal of the product machine, they are computationally expensive. In this paper we present a new method for sequential equivalence checking which utilizes functionally equivalent signals to prove the equivalence of both circuits, thereby avoiding the state space traversal. The effectiveness of the proposed method is confirmed by experimental results on retimed and optimized ISCAS´89 benchmarks
Keywords :
circuit analysis computing; formal verification; integrated logic circuits; logic CAD; sequential circuits; functionally equivalent signals; sequential equivalence checking; verification method; Boolean functions; Circuit synthesis; Data structures; Design automation; Logic; Optimization methods; Registers; Sequential circuits; Space technology; State-space methods;
Conference_Titel :
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-8359-7
DOI :
10.1109/DATE.1998.655922
