Title :
A clock-gating method for low-power LSI design
Author :
Kitahara, Takeshi ; Minami, Fumihiro ; Ueda, Toshiaki ; Usami, Kimiyoshi ; Nishio, Seiichi ; Murakata, Masami ; Mitsuhashi, Takashi
Author_Institution :
Semicond. DA & Test Eng. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
This paper describes an automated layout design technique for the gated-clock design. Two issues must be considered for gated-clock circuits to work correctly. One is to minimize the skew for gated-clock nets. The other is to keep timing constraints for enable-logic parts. We propose the layout design technique to taking these things into consideration. We developed gated-clock tree synthesizer for the first issue, and timing constraints generator and clock delay estimator for the second. We applied it to a practical gated-clock circuit. By our technique, the clock-skew could be less than 0.2 ns keeping timing constraints for enable-logic parts
Keywords :
delays; large scale integration; logic design; logic testing; timing; automated layout design; clock delay estimator; clock-gating method; enable-logic parts; gated-clock circuits; gated-clock design; gated-clock tree synthesizer; low-power LSI design; timing constraints; timing constraints generator; Circuits; Clocks; Design methodology; Electronic design automation and methodology; Large scale integration; Logic; Registers; Signal design; Timing; Tree graphs;
Conference_Titel :
Design Automation Conference 1998. Proceedings of the ASP-DAC '98. Asia and South Pacific
Conference_Location :
Yokohama
Print_ISBN :
0-7803-4425-1
DOI :
10.1109/ASPDAC.1998.669476
